Just brainstorming a software workaround. It seems like you could abuse the division error interrupt, and manipulate the stack pointer from inside its ISR? I assume the division error interrupt can't be interrupted since it is interrupt 0?
That's some funny priority inversion! Reading up on it, the division error interrupt will be processed by the hardware first (pushed to the stack), but then be interrupted by NMI before the ISR runs.
“Interrupt 0” wasn’t its priority, but it’s index. IIRC, the 8086 doesn’t have the concept of interrupt priority. Upon encountering a #DE, the processor would look up interrupt 0 in the IVT (located at 0x00000 though 0x00003 in “real mode”).
