However, from the point of view of these designs, the PLL is an internal black box that allows us to generate an (almost) arbitrary clock frequency.
We choose a frequency to meet I/O or performance requirements. In this case a pixel clock of ~25 MHz: we have to meet this to generate a valid 640x480 video signal.
None of the Exploring FPGA Graphics designs uses a CPU: the logic is all in hardware, often a finite state machine. The trick is ensuring the hardware logic completes within one clock cycle. For 25MHz, each clock cycle is 40ns. If a design is too complex to meet timing, we can break it into multiple steps, similar to pipelining on a CPU[1].
You can also run different parts of a design at different clock frequencies, but this introduces the challenge of clock domain crossing[2].
For a low-end FPGA, like an Artix-7, you can expect to run a reasonably complex design at 100-200 MHz.
However, from the point of view of these designs, the PLL is an internal black box that allows us to generate an (almost) arbitrary clock frequency.
We choose a frequency to meet I/O or performance requirements. In this case a pixel clock of ~25 MHz: we have to meet this to generate a valid 640x480 video signal.
None of the Exploring FPGA Graphics designs uses a CPU: the logic is all in hardware, often a finite state machine. The trick is ensuring the hardware logic completes within one clock cycle. For 25MHz, each clock cycle is 40ns. If a design is too complex to meet timing, we can break it into multiple steps, similar to pipelining on a CPU[1].
You can also run different parts of a design at different clock frequencies, but this introduces the challenge of clock domain crossing[2].
For a low-end FPGA, like an Artix-7, you can expect to run a reasonably complex design at 100-200 MHz.
[1] https://en.wikipedia.org/wiki/Classic_RISC_pipeline
[2] https://en.wikipedia.org/wiki/Clock_domain_crossing