I think X86 is the only modern ISA family that still have a separate address space for I/O. It is not used today anymore, but it exists somewhere deep in the chip, and its legacy kind of messed up how the entire wider memory, and cache systems on X86 were designed.
X86 has got memory mapped I/O for modern hardware, but on the way there, X86 memory access got tangled with bus access. X86 still treats the wider memory system as a kind of "peripheral" with mind of its own.
The intricacies how X86 memory access evolved to keep accommodating decades old drivers, and hardware apparently made a grand mess of what you can, and what you cannot memory map, or cache, and many things deeper in the chip.
One of may casualties of that design decision is the X86 cache miss penalty, and an overall expensive memory operations.
I don't really get what you are talking about. Everybody has been doing MMIO for a while now (and by for a while I mean multiple decades), and IO is usually not an issue in personal computers anyway; OOO, compute and the memory hierarchy is. We are not discussing about some mainframes...
> I think X86 is the only modern ISA family that still have a separate address space for I/O. It is not used today anymore, but it exists somewhere deep in the chip, and its legacy kind of messed up how the entire wider memory, and cache systems on X86 were designed.
Internally it's just a bank of memory these days. You can publicly see how HyperTransport has treated it as a weird MMIO range for decades (just like Message Signaled Interrupts), and QPI takes the same approach.
Why can't they just give the IO bus a slower clock and devote the resources to the memory bus? Or, memory-map everything and make the IO area yet another reserved area the BIOS tells the OS about?
X86 has got memory mapped I/O for modern hardware, but on the way there, X86 memory access got tangled with bus access. X86 still treats the wider memory system as a kind of "peripheral" with mind of its own.
The intricacies how X86 memory access evolved to keep accommodating decades old drivers, and hardware apparently made a grand mess of what you can, and what you cannot memory map, or cache, and many things deeper in the chip.
One of may casualties of that design decision is the X86 cache miss penalty, and an overall expensive memory operations.