It was indeed logic. A pair of MACs, a pair of ALUs, big chunk of on-chip memory and a big ol' mess of wires to interconnect them all. Heavily pipelined. For use in signal processing applications where latency wasn't really a concern.
We dabbled with big image sensor arrays but the sparing for yield was messy and we never came to grips with how to deal with the situation where the working sensors were in random locations in the array. It seemed to really mess up all the important systems level calculations. We also never completely worked out testing. The big logic chip had BILBO blocks so we could just put it in self test mode, run a lot of clock cycles, check the signatures, and switch in the working blocks. The sensor array needed more than that. Perhaps solvable issues, but we never got around to it.
We dabbled with big image sensor arrays but the sparing for yield was messy and we never came to grips with how to deal with the situation where the working sensors were in random locations in the array. It seemed to really mess up all the important systems level calculations. We also never completely worked out testing. The big logic chip had BILBO blocks so we could just put it in self test mode, run a lot of clock cycles, check the signatures, and switch in the working blocks. The sensor array needed more than that. Perhaps solvable issues, but we never got around to it.