[I'm not a microarchitecture expert]

I've read that x86 has multiple registers (eg, https://news.ycombinator.com/item?id=9264195, http://blog.erratasec.com/2015/03/x86-is-high-level-language...). "You want to do something with rax, so the processor grabs one of its 168 internal registers to play the role of rax for a moment" sounds like a type of register-window implementation to me. Or I'm completely misinterpreting the term.

Note that my sentiment/tone in asking this is "huh, if that's the case then POWER and other architectures could really compete with x86!". (Assuming POWER doesn't use that approach.)

You are describing "register renaming". And it's what everybody discovered was a better idea than putting "specific tasks" to registers with windows, banks, etc.

Of course, IBM knew about this way back.

https://en.wikipedia.org/wiki/Tomasulo%27s_algorithm

Those who do not study history are doomed to repeat it.

OoO register renaming is a nearly orthogonal concept compared to SPARC style register windows. And I say nearly, mainly because if you try to implement both it increases the complexity more than you would think due to microarchitectual interactions between the two concepts.

Also, it's not really an x86 thing (for instance most Atoms don't have these extra registers), it's an in-order vs out-of-order thing. Most Power cores do have the larger bank and renaming.

What, specifically, about register windows and delay slots makes them unsuitable for today's needs?

PS: read my profile description.

They complicate OoO core design.