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I read that, but how much, type, architecture, latencies, etc? This is a huge factor in the performance of the chip.


"Each Epyc has 64KB and 32KB of L1 instruction and data cache, respectively, versus 32KB for both in the Broadwell family, and 512KB of L2 cache versus 256KB. AMD says Epyc matches the Broadwells in L2 and L2 TLB latencies, and has roughly half the L3 latency of Intel's counterparts."

https://www.theregister.co.uk/2017/06/20/amd_epyc_launch/

Various L3 sizes in the article.




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