I believe the commenter is referring to system where you take a giant “git sed” and automate a rather complicated process: 1. break up one huge diff into a set of many (hundreds or thousands) patches, where each individual patch only touches files in a particular subsystem. 2. send all those patches to the appropriate system owners and run the appropriate tests. 3. manage the actual merging of successful patches, as well as communicating to the original author any individual patches that might need more attention e.g. based on patch review feedback.
as you might imagine, it’s probably a pretty involved process to touch thousands of lines of code in a complicated system.
It’s a frustrating essay, because it comes close to having a helpful message. A phrase like “being engaged” seems closer to what he tries to get across, but a lot of young people will probably mostly take from this essay that they need to hustle, which is the kind of useful advice you’ll hear from a high school guidance counselor.
One must not forget that PG has an agenda to push just like every other influencer. I believe he was specifically aware of his use of hustle culture language.
The DMCA has a (de facto toothless) perjury clause for knowingly submitting a takedown for content that doesn’t violate the copyright of the claimant. That doesn’t apply to YouTube claims that are handled via their internal tools outside of the DMCA process.
>They mention “performance/area” as being dramatically better than Cortex-A75.
The P550 pref / area based on Intel 7nm equivalent to TSMC 4nm / 3nm that is better than the ARM Cortex A75 released in 2017 on TSMC 10nm.
Number using Intel CPU's 7nm, normally Custom Foundry of IFS tends to offer lower density but higher flexibility. So this is more like a best case scenario.
I am also suspicious of the Intel 7nm number. There are some possibility this is actually an Intel 10nm renamed to 7nm for custom foundry partners. ( Intel 10nm being equivalent to TSMC 7nm )
No, the area numbers quoted are for TSMC N7. You can look up comparable A75 die area numbers for N7 as well. A Cortex A76 on TSMC N7 takes up 1.27mm with L2 included. A P550 takes up 0.38mm.
As per Intel announcement and Anandtech [1] while not explicityly stated, the P550 number are from Intel 7nm Intel Foundry Services. I am not sure where that TSMC N7 came from.
SiFive likes to include just enough resources to do well on their benchmark du jour (was dhrystone, now SPECint) and leave out the rest. So they end up comparing an Arm core with NEON against their RISC-V cores with no SIMD/vector support for example.
Previous cores had no vector support because the V extension that provides for it was nowhere close to being standardized. In fact it's yet to be ratified at present, so one may want to wait for that before choosing a V-capable core for real, actual use.
Which is fine because what would normally be handled by the SIMD will be custom silicon for most customers and have a 4-100x speedup over what SIMD could provide.
perf/area comes with a huge number of caveats and it basically doesn't mean anything as given.
For example, the exact same verilog, on the same process node at the same foundry, can synthesize to very different areas depending on the standard library used. They come in a lot of varieties with a lot of different trade offs.
For even more detail, the SkyWater130 node, which has been popular on HN lately and is public so we can actually post links to it, has 6 different mappings that are possible. Note, some are called high speed, or high density, etc. You get the idea.
I'm not even why we're supposed to care about a newly launched core beating one that was released in 2017. If that's the bar they've set, I'm not exactly wowed.
Look at the trajectory for ARM catching up with Intel. The trajectory for RISC-V is even faster. That’s at least mildly indicative of where the future is headed.
The first 4 minute mile record was set in 1954. Now there are a bunch of people who have done it. Once formerly new techniques start to be known and distributed, it becomes much easier to catch up.
Remember, RISC-V doesn't have to beat ARM -- only come close enough that the price differential outweighs the performance difference. This is already happening on the low-end end and it's only a matter of time (IMHO) before this becomes reality on the high-end too.
Not every task requires the latest and fastest CPU. ARM makes and sells a huge number of smaller slower lower power cores -- numerically far more than the high end cores in SmartPhones -- and RISC-V is there competing with all but the very high end.
Apparently the overwhelming majority of HN audience doesn't really know how the basics of what a stock exchange functionally does (including myself). I'm starting from here, "Getting to Know the Stock Exchanges"...
Anyway, maybe a good question for someone familar with the technical details - why is there so much volume already flowing through LTSE? Is it just arbitrarily included in some standard broker software application such that it doesn't make a difference to them? Since apparently there is already nearly as much volume traded on LTSE as there is through Nasdaq.
What kind of background do you need to understand a decent amount of this tech? I basically only understand software and there seem to be many different areas advanced in this product.
Maybe the kind of answer I'm looking for is: are there any documented DIY projects that touch some of the tech used here?
DOI: 10.1016/j.medj.2025.100887